Generally, a system including a multi-track digital signal reproducing apparatus is arranged as shown in FIG. 1. In the figure, the analog signal reproduced by a reproduction head RH of each track is amplified by a reproduction amplifier RA to have a sufficient voltage level needed for binary conversion, and then converted into binary data by a data detection circuit DD. Thereafter, the binary data in the form of digital modulation for the purpose of digital recording is demodulated back to the original binary data by a demodulator DM. Then, the serial binary data is converted into parallel data by a serial-to-parallel converter S/P, and after the data of each track has been subjected to error correction by an error corrector CC, it is converted back to the original analog signal by a D/A converter and sent out from the system. In FIG. 1, the arrows marked by "//" represent multiple signal lines, and the remaining arrows represent single signal lines.
The serial-to-parallel converter S/P is generally designed so that the variation in the bit rate of reproduced data caused by the variation of the tape speed is modified. One example of the demodulator DM and serial-to-parallel converte S/P in FIG. 1 is disclosed, for example, in Japanese Patent Application Laid-open No. 57-135413, and this is shown in FIG. 2. The arrangement shown in the figure includes a reproduction circuit 10, a PLL reproduction clock circuit 12, a demodulation circuit 14, a write address counter 20, memories 22, 24 and 26, multiplexers 28, 30, 32, 34 and 44, a read address counter 38, a read frame address counter 40, and a track selection counter 46.
In FIG. 2, the reproduction circuit 10 digitizes the signal reproduced by the magnetic head. The PLL reproduction clock circuit 12 reproduces the clock which is in synchronism with the reproduced signal. The demodulation circuit 14 retrieves the original digital data from data digitized by the reproduction circuit 10. The frame synchronizing signal is detected in the demodulated data. The demodulated data and frame synchronizing signal are sent out over the lines 16 and 18, respectively.
The write address counter 20 produces address data based on the reproduced clock, and specifies the write address of the timing correction memories 22, 24 and 26. The multiplexers 28, 30 and 32 specify the read/write mode and switch the address specification accordingly. The read address counter 38 produces the reading address based on the reference clock with extremely small timing variation received on the line 36. The frame address counter 40 generates the frame address.
In the case of a multi-track system, block 48 including the above-mentioned components referred to by numerals 10 through 32 is needed corresponding to each track as shown simply by blocks 48a, 48b and 48c. Outputs 42, 42a, 42b and 42c from the respective tracks are fed to the track switching multiplexer 44. A track to be read is designated by the track read counter 46.
The operation of the foregoing arrangement will be described in the following. The multiplexers 28, 30 and 32 set up the respective memories in write or read mode in response to the frame synchronizing signals provided by the demodulation circuit 14. As shown in FIG. 3, the Nth frame synchronizing signal sets up the memories 24 and 26 in read mode, and the memory 22 in write mode. Subsequently, the N+1st frame synchronizing signal sets up the memory 24 in write mode, and the memory 26 in read mode. Next, the N+2nd frame synchronizing signal sets up the memories 22 and 24 in read mode, and the memory 26 in write mode. These three states of memory are cycled in every three frame synchronizing periods. It should be noted, however, that the aforementioned procedure is merely an example, and the transition from read mode to write mode does not necessarily occur at each synchronizing signal, but it depends on the degree of jitter of the recording apparatus and the capacity of memory. For example, the mode setup operation may take place at other frame intervals such as 2-frame or 3-frame intervals.
One frame of data is written in the memory which has been set to write mode, and this memory is set to read mode for a 2-frame period in response to the subsequent frame synchronizing signal. In the read mode, the memory is read out using the above-mentioned reference clock. The reference clock is derived from a high frequency signal with extremely high frequency stability generated by use of a crystal oscillation element. Accordingly, the timing variation of the reference clock is extremely small.
Upon completion of writing, one frame of data which has been written previously is read out with a delay of 1/2 to 1+1/4 frames so that the reading will complete 1/2 frame in advance of the next writing. Namely, by use of three memories in parallel for each track, the timing variation can be corrected with a margin of 1/2 frame against jitter.
In the conventional circuit arrangement as described above, a plurality (generally three or more) of memories for the correction of timing variation are needed for each track. The number of memories needed is further increased by N-fold when the apparatus is designed for multi-track capability. This results in an expanded circuit arrangement, precluding the objectives of compactness, low power dissipation and cost reduction of the apparatus.